1. Technical Field
The present disclosure relates to a data receiver and more particularly, to a clock and data recovery (CDR) circuit recovering clocks and data from a data signal of a high frequency and a method of recovering clocks and data.
2. Discussion of Related Art
In general, in order to transfer data at high speed between a transmitter and a receiver that are spaced apart from each other, a receiver has to exactly extract the data from a received data signal. For example, data may be extracted by sampling a received data signal using a clock signal of a frequency that is the same as a carrier frequency of the received data signal.
Typically, such a clock signal is transmitted with a data signal from a transmitter, and a receiver receives the clock signal and the data signal and extracts data by sampling the data signal based on the received clock signal.
According to conventional methods, a clock generation circuit is needed to generate a clock signal in a receiver, and a transmission line, an input pin, and an output pin that are exclusively used are needed for transmitting the clock signal between a transmitter and a receiver. As data transmission systems require faster operating speeds and lower operating voltages, however, the conventional methods for transmitting a clock signal and a data signal through respective transmission lines cause various problems, such as signal skews, jitter, noise, and the like. Therefore, additional efforts for optimizing a physical arrangement of transmission lines are needed to synchronize a data signal with a clock signal and to reduce jitter and noise.
According to a conventional clock and data recovery method, a clock signal is recovered from a data signal without the additional transmission of a clock signal. Therefore, a clock generation circuit is not used in a receiver. A transmission line, an input pin, and an output pin that are exclusively used to transmit the clock signal are unnecessary. Therefore, it takes less effort to synchronize a data signal with a clock signal, so as to reduce jitter and noise.
A basic configuration of a conventional clock and data recovery circuit is similar to a configuration of a phase locked loop circuit, but a data signal instead of a reference frequency is used to recover a clock signal. The clock and data recovery circuit, which is similar to the phase locked loop circuit, includes a phase-frequency detector. The phase-frequency detector compares a phase and a frequency of a received data signal with those of a recovered clock signal.
FIG. 1 is a diagram illustrating a conventional phase-frequency detector used for clock and data recovery,
Referring to FIG. 1, the phase-frequency detector 10, which is known as a Hogge phase detector includes two D flip-flops 11 and 12 that are connected in series to detect whether the phase of a clock signal CLK leads or lags the phase of a data signal DATA,
The first D flip-flop 11 may compare a rising edge of the data signal DATA with a rising edge of the clock signal CLK, and a second D flip-flop 12 may compare a falling edge of the data signal DATA with a falling edge of the clock signal CLK. The comparison results may be provided to a charge pump as an up signal UP and a down signal DOWN, respectively.
The Hogge phase detector 10 has a simple configuration so that the Hogge phase detector 10 operates reliably, but the Hogge phase detector 10 has some problems which are as follows. As a data transmission rate rises, the clock signal that is applied to the D flip-flops has a higher frequency. A practical D flip-flop has a limitation in operating speed, however and the higher frequency of the clock signal causes a problem such that a static skew is increased. Moreover, the Hogge phase detector has unstable response characteristics when a data signal contains a large amount of noise, and an output frequency is adversely affected by transitions of the data signal.